FORWARD BODY-BIAS MOS (FBMOS) DUAL RAIL LOGIC USING AN ADIABATIC CHARGING TECHNIQUE WITH SUB-0.6-V OPERATION

Authors
KIOI K KOTAKI H KAKIMOTO S FUKUSHIMA T SATO Y
Citation
K. Kioi et al., FORWARD BODY-BIAS MOS (FBMOS) DUAL RAIL LOGIC USING AN ADIABATIC CHARGING TECHNIQUE WITH SUB-0.6-V OPERATION, Electronics Letters, 33(14), 1997, pp. 1200-1201
Citations number
7
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
33
Issue
14
Year of publication
1997
Pages
1200 - 1201
Database
ISI
SICI code
0013-5194(1997)33:14<1200:FBM(DR>2.0.ZU;2-G
Abstract
A novel logic family for low-voltage adiabatic logic, called forward b ody-bias MOS (FBMOS) dual rail logic, has been proposed. This techniqu e uses forward body-bias effects to enable non-floating output levels during the entire data valid time without increased transistor count.