1T1C FRAM with ferro-programmable redundancy scheme

Designers have tried to find a technology that will give the non-volatility of SRAM with the size and speed of DRAM for some time. FRAM has been a pop ular area of research, but until now has not been able to compete because t he technology used two transistors and two capacitors (2T2C), For higher de nsity, a single transistor, single capacitor (1T1C) architecture would need to be used, but before this architecture can be used a couple of problems have to be ironed out. This article discusses how these might be overcome.