This paper investigates the potential of self-timed property of differentia
l cascode voltage switch logic (DCVSL) circuits, and examines architectural
techniques for achieving self-timing in DCVSL circuits. As a result, a fas
t and robust handshake scheme for dynamic asynchronous circuit design is pr
oposed. It is novel and more general than other similar schemes. The propos
ed self-timed datapath scheme is verified by an 8-bit divider which is impl
emented using AMS 0.6-mum CMOS technology, and the chip size is about 1.66
mm X 1.70 mm, The chip testing results show that the divider functions corr
ectly and the latency for 8-bit quotient-digit generation is 17 ns (about 5
8.8 MHz).