Low-power digital matched filter for direct-sequence spread-spectrum signal acquisition

This paper presents a low-power 128-tap dual-channel direct-sequence spread -spectrum (DSSS) digital matched-filter chip. Design techniques used to red uce the power consumption of the system include latch-based register file f ilter structure, a high-rate compression scheme, optimized compressor cells , and semicustom layout design. To further reduce the power consumption and the hardware requirement of the clock tree, a double-edge-triggered clocki ng scheme is adopted. The proposed chip is fabricated using a 0.8-mum stand ard CMOS process. As the experimental results of the chip indicate, the mat ched filter can operate at 50 MHz and dissipates 184 mW at 5-V supply volta ge. The supply voltage can be scaled down to 2 V for lower speed applicatio ns. As a consequence, the proposed design has low power consumption and can be used for code acquisition of DSSS signals in portable systems.