1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-mu m CMOS

This paper describes the design and the implementation of input-output (I/O ) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-mum CMOS technology in a couple of test chips. The transmitter is fully compatible (dc coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the volta ge-switching principle in order to allow different termination schemes besi des the canonical ECL termination, i.e., 50-Omega toward (V-DD - 2) V. The addition of some circuit techniques such as dynamic biasing and strobed cur rent switching boosts the dynamic performance of the basic voltage-switchin g scheme and relaxes the requirements for a high bias current and large-siz e output devices at the same time. Moreover, thanks to the developed refere nce circuit, using both feedforward and feedback controls, the output level s are within the 100K tolerance over the full range of process, supply volt age, and temperature (PVT) variations without resorting to external compone nts or on-chip trimming, The receiver cell is based on a complementary-diff erential architecture providing high speed and low error on the duty cycle of the CMOS output signal, The integrated receiver-transmitter chain exhibi ts a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission l ink using the developed I/O interface was tested up to 1.2 Gb/s.