Long unsigned number systolic serial multipliers and squarers

A systolic serial multiplier and a squarer for unsigned numbers-which opera te without zero words inserted between successive data words, output the fu ll product, and have only one clock cycle latency-are presented. The multip lier is based on a modified serial/parallel scheme that operates with 100% efficiency. The systolic form is obtained by merging two adjacent multiplie r cells. The same technique is used for the design of a serial squarer. The systolisity and the continuous operation are achieved without an increase in hardware complexity. The proposed schemes are well suited for long numbe r multiplication and squaring.