Compact CMOS implementation of a low-power, current-mode programmable cellular neural network

We report on the design and characterization of a full-analog programmable current-mode cellular neural network (CNN) in CMOS technology. In the propo sed CNN, a novel cell-core topology, which allows for an easy programming o f both feedback and control templates over a wide range of values, includin g all those required for many signal processing tasks, is employed. The CMO S implementation of this network features both low-power consumption and sm all-area occupation, making it suitable for the realization of large cell-g rid sizes. Device level and Monte Carlo simulations of the network proved t hat the proposed CNN can be successfully adopted for several applications i n both grey-scale and binary image processing tasks. Results from the chara cterization of a preliminary CNN test-chip (8 x 1 array), intended as a sim ple demonstrator of the proposed circuit technique, are also reported and d iscussed. Copyright (C) 2001 John Wiley & Sons, Ltd.