Analysis and optimization of a novel CMOS multiplier

A novel CMOS voltage multiplier is proposed which is based on MOS transisto rs in the saturation region and uses a resistor load. A pencil-and-paper op timized design procedure and a detailed analysis of second-order non-ideali ties which affect the multiplier core are given. The circuit has been desig ned with a 1.2 mum CMOS process setting a 3V power supply and simulations h ave been performed to validate results. Copyright (C) 2001 John Wiley & Son s, Ltd.