Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec

Several parallel, pipelined and folded architectures with different through put rates are presented for computation of DCT, one of the fundamental oper ations in image/video coding. This paper begins with a new decomposition al gorithm for the 1-D DCT coefficient matrix. Then the 2-D DCT problem is con verted into the corresponding 1-D counterpart through a regular index mappi ng technique. Afterward, depending on the trade-off between hardware comple xity and speed performance, the derived decomposition algorithm is transfor med into different parallel-pipelined and folded architectures that realize the butterfly operations and the post-processing operations. Compared to o ther DCT processor, our proposed parallel-pipelined architectures, without any intermediate transpose memory, have the features of modularity, regular ity, locality, scalability, and pipelinability, with arithmetic hardware co st proportional to the logarithm of the transform length.