Multimedia execution hardware accelerator

In this paper we show that some expressions frequently used in multimedia a pplications can be formulated as a general add-multiply-add operation. We f urther show a hardwired implementation of the Add-Multiply-Add instruction which is no more complex than the multiplier implementation. Furthermore we show that two frequently motion estimation operations, the Sum and Mean of Absolute Differences, can be implemented in hardware requiring also approx imately the same cycle time as the multiplication. We also show that our ap proach can be extended easily to provide the computation of the Sum and Mea n of Absolute Difference of a 16x16 pixel block in no more than four machin e cycles. Additionally we propose a codec hardwired mechanism for the Paeth predictor used in the Portable Network Standard (PNG) that requires at mos t two general purpose ALU cycles. We extend the paeth unit to include the m edian, maximum and minimum operations on three inputs with no additional cy cle time and we also extend the Add-Multiply-Add unit to include the mean o f three numbers. Finally we propose a multimedia hardware accelerator to ac commodate all the proposed operations. The proposed unit is an extension of the multiply pipeline with ALU extensions with no extra stages added. The unit operates on 32 instructions in total.