CONTROLLED 2-STEP SOLID-PHASE CRYSTALLIZATION FOR HIGH-PERFORMANCE POLYSILICON TFT

Citation
V. Subramanian et al., CONTROLLED 2-STEP SOLID-PHASE CRYSTALLIZATION FOR HIGH-PERFORMANCE POLYSILICON TFT, IEEE electron device letters, 18(8), 1997, pp. 378-381
Citations number
13
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
07413106
Volume
18
Issue
8
Year of publication
1997
Pages
378 - 381
Database
ISI
SICI code
0741-3106(1997)18:8<378:C2SCFH>2.0.ZU;2-N
Abstract
Solid-phase crystallization For polysilicon thin-film transistors (TFT 's) is generally limited by a tradeoff between throughput and device p erformance. Larger grains require lower crystallization temperatures, and hence, longer crystallization times. In this letter, a novel cryst allization technique is presented which increases both throughput and device performance, using a tyro-step process, controlled using an in situ acoustic temperature/crystallinity sensor. A high-temperature rap id thermal annealing (RTA) nucleation step is followed by a low-temper ature grain growth step to grow large-grain polysilicon. TFT's have be en Fabricated with a substantial improvement in throughput and device performance. This promises a high-throughput, high-performance, spatia lly uniform TFT process.