FABRICATION AND CHARACTERIZATION OF AN INALAS INGAAS/INP RING OSCILLATOR USING INTEGRATED ENHANCEMENT-MODE AND DEPLETION-MODE HIGH-ELECTRON-MOBILITY TRANSISTORS/

Citation
A. Mahajan et al., FABRICATION AND CHARACTERIZATION OF AN INALAS INGAAS/INP RING OSCILLATOR USING INTEGRATED ENHANCEMENT-MODE AND DEPLETION-MODE HIGH-ELECTRON-MOBILITY TRANSISTORS/, IEEE electron device letters, 18(8), 1997, pp. 391-393
Citations number
14
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
07413106
Volume
18
Issue
8
Year of publication
1997
Pages
391 - 393
Database
ISI
SICI code
0741-3106(1997)18:8<391:FACOAI>2.0.ZU;2-G
Abstract
The fabrication and characterization of an 11-stage ring oscillator ut ilizing integrated enhancement- and depletion-mode (E/D-mode) high-ele ctron mobility transistors (HEMT's) in the lattice-matched InAlAs/InGa As/InGaAs material system is demonstrated. The 0.5-mu m gate length de pletion-mode HEMT's (D-HEMT's) used in the circuit exhibit a threshold voltage (V-T) of -365 mV with a standard deviation of 19 mV, while th e enhancement-mode HEMT's (E-HEMT's) with identical gate length displa y a V-T of 195 mV with a standard deviation of only 9 mV. The unity cu rrent gain cutoff frequency (f(t)) for both devices is 70 GHz. The ext remely high uniformity of the threshold voltages of these devices allo wed for the implementation of a ring oscillator utilizing direct coupl ed FET logic (DCFL). At a supply voltage of 0.4 V, a room temperature propagation delay time (tau(pd)) of 22.4 ps/stage, and a corresponding power dissipation of 120 mu W/stage is measured, yielding a power del ay product (PDP) of 2.65 fJ/stage. To the best of the authors' knowled ge, this is the first demonstration of a circuit employing E/D-HEMT te chnology in the lattice-matched InP-based material system.