Novel cell transistor using retracted Si3N4-Liner STI for the improvement of data retention time in gigabit density DRAM and beyond

In this paper, we propose a novel cell transistor using retracted Si3N4-lin er STI for the enhanced and reliable operation of 256-Mb dynamic random acc ess memory (DRAM) in 0.15-mum technology. As the technology of DRAM has bee n developed into the sub-quarter-micron regime, the control of junction lea kage current at the storage node is much more important due to the increase d channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si3N4-liner, the inverse narrow widt h effect (INWE) was significantly reduced. The channel doping concentration , hence, was lowered without degrading the subthreshold leakage characteris tics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data re tention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-mum technology and be yond.