Low-frequency noise of integrated poly-silicon resistors

This paper presents an analytical first principle model for the low-frequen cy noise current of poly-silicon layers used as resistors in analog CMOS ap plications. The observed noise is much higher than predicted by the models mostly used in circuit simulation. The dependence on specific processing pa rameters such as doping or deposition techniques are investigated and expla ined. The model is confirmed by measurement of deviations in the flicker no ise behavior of small size resistors. Guidelines for analog circuit design and a noise model for circuit simulation are presented.