Impact of CMOS processing steps on the drain current kink of NMOSFETs at liquid helium temperature

The impact of certain CMOS processing steps on the drain current kink in nM OSFETs fabricated in a 0.7-mum technology and operated at liquid helium tem peratures (LHTs) is investigated. The kink is successfully suppressed when implementing a lowly-doped drain (LDD) or a p-well, while the application o f a threshold voltage adjust implantation has a more subtle effect. In orde r to understand the observations in more detail the impact ionization rate in the different splits is analyzed, whereby particular efforts are spent t o accurately determine the saturation drain voltage V-DSAT from the 4.2 K o utput characteristics. An optimized method based on the extrapolation of th e output resistance yields consistent data and a critical field for inversi on layer velocity saturation of (1.2 +/- 0.1) x 10(4) V/cm at 4.2 K. It wil l finally be demonstrated that a high-energy room-temperature proton irradi ation has a qualitatively similar beneficial effect on the kink as the use of an LDD, for example.