FPGA prototyping of a RISC processor core for embedded applications

Citation
M. Gschwind et al., FPGA prototyping of a RISC processor core for embedded applications, IEEE VLSI, 9(2), 2001, pp. 241-250
Citations number
22
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN journal
10638210 → ACNP
Volume
9
Issue
2
Year of publication
2001
Pages
241 - 250
Database
ISI
SICI code
1063-8210(200104)9:2<241:FPOARP>2.0.ZU;2-4
Abstract
Application-specific processors offer an attractive option in the design of embedded systems by providing high performance for a specific application domain, In this work, we describe the use of a reconfigurable processor cor e based on an RISC architecture as starting point for application-specific processor design. By using a common base instruction set, development cost can be reduced and design space exploration is focused on the application-s pecific aspects of performance. An important aspect of deploying any new architecture is verification which usually requires lengthy software simulation of a design model. We show ho w hardware emulation based on programmable logic can be integrated into the hardware/software codesign flow While previously hardware emulation requir ed massive investment in design effort and special purpose emulators, an em ulation approach based on high-density field-programmable gate array (FPGA) devices now make hardware emulation practical and cost effective for embed ded processor designs. To reduce development cost and avoid duplication of design effort, FPGA pro totypes and ASIC implementations are derived from a common source. We shaw how to perform targeted optimizations to fully exploit the capabilities of the target technology while maintaining a common source base.