A hardware cost minimized fast Phong shader

Citation
Hc. Shin et al., A hardware cost minimized fast Phong shader, IEEE VLSI, 9(2), 2001, pp. 297-304
Citations number
12
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN journal
10638210 → ACNP
Volume
9
Issue
2
Year of publication
2001
Pages
297 - 304
Database
ISI
SICI code
1063-8210(200104)9:2<297:AHCMFP>2.0.ZU;2-0
Abstract
One of the most successful algorithms that bring realism to the world of th ree-dimensional (3-D) image generation is the Phong shading, With the conti nuous improvement in VLSI technology and the demand for higher realism, thi s algorithm is a menable to the commercially available hardware implementat ion for real-time rendering in 3-D graphics. Taylor series approximation is appropriate for the hardware implementation of fast Phong shading. However , in this method, the exponentiation of the cosine term requires a very lar ge ROM table, This paper describes the minimization of this overhead in ter ms of hardware size by proposing an adaptive-compressed nonuniform quantiza tion method. With this method, the ROM table is reduced to 1/64th of the si ze required for a uniform quantization method while the picture quality is maintained. Due to the reduced ROM table size, the size of the total hardwa re required for fast Phong shading is minimized to 1/56th of the original s ize.