Vector generation for power supply noise estimation and verification of deep submicron designs

This paper presents new techniques for generating a small set of patterns f or power network simulation to estimate the maximum power supply noise of t he chip, as well as to identify cells/blocks for which the power supply noi se at their V-dd ports exceeds a specified threshold. We first present an e fficient, cell-level simulator for estimating power supply noise of any giv en vectors. Based on this simulator, we then apply the genetic algorithm (G A) to derive a small set of patterns producing high power supply noise. To identify critical nodes with power supply noise exceeding a threshold, the multiobjective GA is adapted for pattern generation, To achieve high covera ge of such critical nodes, we model the search criteria as the maximum weig hted matching of a bipartite graph, and guide the search direction accordin g to the matching results. The derived patterns will be simulated on a powe r network simulator to obtain a lower bound of the maximum power supply noi se and to identify the critical nodes. Experimental results on public bench mark circuits, as well as some industrial designs, are presented to demonst rate the efficiency and effectiveness of the proposed approaches.