Fast floorplanning for effective prediction and construction

Floorplanning is a crucial phase in VLSI physical design. The subsequent pl acement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is simu lated annealing. It gives very good floorplanning results but has major lim itation in terms of run time. For circuit sizes exceeding tens of modules s imulated annealing is not practical. Floorplanning forms the core of many s ynthesis applications. Designers need faster prediction of system metrics t o quickly evaluate the effects of design changes. Early prediction of metri cs is imperative for estimating timing and routability, In this work we pro pose a constructive technique for predicting floorplan metrics. We show how to modify the existing top-down partitioning-based floorplanning to obtain a fast and accurate floorplan prediction. The prediction gets better as th e number of modules and flexibility in the shapes increase. We also explore applicability of the traditional sizing theorem when combining two modules based on their sizes and interconnecting wire-length. Experimental results show that our prediction algorithm can predict the area/length cost functi on normally within 5-10% of the results obtained by simulated annealing and is, on average, 1000 times faster.