Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (C MOS) circuit for a dual-threshold voltage process. The tradeoff between sta tic and dynamic power consumption has been explored. When used along with d evice sizing and supply voltage reduction techniques for low power, the pro posed algorithm can reduce the total power dissipation of a circuit by as m uch as 50%.