A high-speed low-power divide-by-15/16 dual modulus prescaler in 0.6 mu m CMOS

A new high-speed low-power dual modulus prescaler (DMP) topology is propose d. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4 /5 divider, it has a higher speed by eliminating the NAND-gate introduced c ritical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFF's) required. Based on this topo logy, a divide-by-15/16 DMP is implemented in the 0.6 mum standard CMOS pro cess. Simulation result shows that a maximum operating frequency of 2.15 GH z is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circ uit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltag e with 570 MHz input frequency.