Computational parameter study of chip scale package array cooling

This paper describes the results of a computational investigation into the thermal management of chip scale package arrays, The parameters considered include power dissipation, cooling air inlet velocity, module spacing, and circuit board conductivity. The geometry used throughout the study was an a rray of five modules placed on board with forced air fooling along the axis of the array both above and below the circuit board. Each module was the s ame size and dissipated the same amount of power Free convection was includ ed with gravity aligned normal to the plane of the circuit board. The effec ts of thermal radiation were neglected and the flow was considered to be la minar. Three dimensional solutions were generated using the commercial comp utational fluid dynamics code FLOTHERM.(1) Results are presented in the form of thermal resistances for each package i n the array, a number of interesting results were found, For the case of lo w conductivity circuit hoards, the resistance for the first package in the array was a function of inlet velocity only. However, this was not the case when power planes were present and energy was conducted more effectively a long the board. For low inlet velocities, when there are strong natural con vection effects, there was a temperature overshoot where the highest temper ature does not occur in the last package of the; array. Finally, when the e ffects of natural convection were small, the thermal resistance was relativ ely insensitive to the power dissipation.