Overview and trend of chain FeRAM architecture

A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and highspeed nonvolatile memory. One memory cell consi sts of one transistor and one ferroelectric capacitor connected in parallel , and one memory cell block consists of plural cells and a block selecting transistor in series. This configuration realizes small memory cell of 4F(2 ) size and fast random access time. This paper shows an overview and trend of chain FeRAM architecture. First, the concept of chain FeRAM is presented , and basic operations including two cell-plate driving schemes are discuss ed. Second, assuming multi-megabit generation, ideal features and performan ces are discussed in terms of die size, speed and other aspects. Third, the prototype of chain FeRAM and the practical cell structure for megabit-scal e memories using 0.5 mum 2-metal CMOS process are demonstrated. By introduc ing fast and compact cell-plate drive technique, this prototype achieves ra ndom access time of 37-ns and read/write cycle time of 80-ns, which are the fastest speeds reported for FeRAMs. Fourth, after discussing future memory cell trend and problems respecting scaled FeRAMs, a gain cell block approa ch for future gigabit-scale chain FeRAMs is introduced. This realizes both a small average cell size and a large cell signal even at small cell polari zation.