Modeling electromigration and the void nucleation in thin-film interconnects of integrated circuits

The modern tendency for increasing the productivity of microelectronic devi ces at the expense of the size shrinkage and the development of densely pac ked multilevel microelectronic structures stipulates the rising concern for the reliability of integrated circuits. The damage of integrated circuits is mainly caused by electromigration in thin-film interconnects. The curren t-induced redistribution of vacancies and the action of vacancy sinks/sourc es lead to heterogeneous volume deformations, which, in turn, cause the ris e of mechanical stresses. The interconnect failure is initiated by the nucl eation of voids taking place on the crystalline structure heterogeneities l ike triple points, inclusions, etc. or in the plug region of multilevel met allizations. In the latter case the interconnect damage is also caused by t he edge depletion. Mechanical stresses induced by electromigration strongly influence the nucleation process. In the present work we propose a general 3D model for electromigration and the rise of mechanical stresses in a pas sivated aluminum interconnect. A system of differential equations describin g electromigration and induced deformation of an interconnect is derived. W e also propose a kinetic model for the void nucleation, elaborated on the b asis of the classical theory of the new phase nucleation. Integral equation s for the time to the void nucleation are deduced. Based on these models nu merical calculations for the void formation in a triple point of the interc onnect crystalline structure and for both failure mechanisms in the plug re gion have been carried out. The times to nucleation and characteristic size s of voids are calculated as functions of temperature and electric current density. The results obtained agree well with experimental data.