PERFORMANCE ANALYSIS OF A REGISTER INSERTION RING WITH A VARIABLE SIZE BUFFER

There has been a recent revival of interest in the register insertion (RI) protocol because of its high throughput and low delay characteris tics. Several variants of the protocol have been investigated with a v iew to integrating voice and data applications on a single local area network (LAN). In this paper the performance of an RI ring with a vari able size buffer is studied by modelling and simulation. The chief adv antage of the proposed scheme is that an efficient but simple bandwidt h allocation scheme is easily incorporated. Approximate formulas are d erived for queue lengths, queueing times, and total end-to-end transfe r delays. The results are compared with previous analyses and with sim ulation estimates. The effectiveness of the proposed protocol in ensur ing fairness of access under conditions of heavy and unequal loading i s investigated. (C) 1997 by Elsevier Science Inc.