A 13-mW 2-GHz/520-MHz dual-band frequency synthesizer for PCS applications

A low-power 13-mW 2.0-GHz/520-MHz RF/IF dual-band integer-N frequency synth esizer is presented. which is based on a pulse swallow technique. The synth esizer has two improved features: an improved dead-zone-free PFD (phase fre quency detector) and a low-pourer design in the ECL(emitter coupled logic) prescaler and the charge pump circuit. The improved PFD is dead-zone-free i ndependent of temperature. supply voltage, and process parameter variation other than previously reported ones using delay elements and results in low er reference spurs and in-band phase noise. For the low-power design, the m aximum operating frequency of the ECL prescaler is optimized over its bias current and a charge-pump enable-control circuit for a dynamic biasing is a dded to the charge pump. The PLL(phase locked loop)-based frequency synthes izer, with an external VCO(voltage controlled oscillator) and a third-order loop filter, achieves an in-band phase noise of -55.25 dBc/Hz at a carrier frequency of 1630 MHz and reference spurs of -70.8 dBc at a 10-kHz offset. The channel switching time Is to ms over the 25-MHz frequency transition w ith a 500 Hz loop-bandwidth. The chip operates at a low operating current o f 4.5 mA in the power supply range of 2.7 similar to 4.0 V. All required sp ecifications for a PCS cell phone based on the IS-95A standard are met. The proposed synthesizer has been fabricated in a 0.5-mum 15 GHz-f(t) BiCMOS t echnology.