Numerical method for extracting parasitic capacitance from multilevel conductors: Stacked DRAM structure

This paper reports a numerical method for extracting parasitic capacitance and its application to multilevel conductors on a semiconductor wafer. The method includes steps transforming the drawn mask layout into a three-dimen sional structure from a physics-based simulation in accordance with the pro cess recipe, and extracting device parameters by using a numerical techniqu e, In order to produce a three-dimensional structure from the mask layout d ata, a topography simulation is undertaken in accordance with the given pro cess recipe comprising various depositions and etching process steps. A fin ite element method (FEM) is employed for calculating: the potential distrib ution and extracting device parameters present in a cell capacitor and inte rvening interlayer dielectric concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 mum was chosen as a test vehicle to check th e validity of the simulation. In this work;. 62 parasitic capacitances and 4 cell capacitances were extracted from a stacked DRAM cell structure over a hit line.