Modeling and simulation of a DRAM cell capacitor with multiple-level interconnects

We report a novel method for 3D modeling of a complex structure on a substr ate for gigabit DRAMs and its implementation into a topography simulator, t he so-called 3D-SURFILER (SURface proFILER). The 3D-SURFILER is comprised o f a plasma/sputter deposition module and an etching process simulator and e mploys a cell-advancing scheme for modeling the evolution of the surface. A level set algorithm is proposed for accurate modeling of the deposition/et ching profile anti the computational efficiency. In this work, a Monte Carl o approach is employed to calculate the distribution of incident ions and s puttered particles. Contact hole structures with different aspect ratios, a s well as a DRAM cell with art MIM (metal-insulator-metal) stacked capacito r, were investigate with the 3D-SURFILER.