New integration technology of a cell landing pad for the 0.13-mu m DRAM generation and beyond

A novel memory cel landing pad technology is developed for the 0.13-mum DRA M (dynamic random access memory) generation and beyond. Compared to convent ional landing pad technology, this novel cell landing pad technology achiev es a lower contact resistance between the contact pad and the source/drain of the memory cell transistor and better isolation between the word-line an d the contact pads. The low-temperature interlayer dieletric process with g ap-fill capability is achieved in this work by using a multi-step depositio n with a high-density plasma chemical vapor deposition oxide. the tight ali gnment tolerance, which can not be met in the conventional scheme., is achi eved by using a novel bar-type contact hole opening pattern and a wet dip p rocess in this technology. Moreover, we adopted the modified SAC (self-alig ned contact) process, in which SAC etching is followed by word-line spacer formation. With this modified SAC process, we could reduce the loss due to the capping nitride on the word-line. Thus, we could solve the problem of i solation between the word-line and the counter pads. the superior propertie s of this novel landing pad technology were demonstrated with the 0.13-mum DRAM generation.