Study of memory cell transistors using a RTA process for giga-bit scale DRAMs

As DRAM technology advances beyond the 0.18-mum technology generation, many issues such as reduced current driving capability, increased gate and diff usion resistance, large fluctuations of threshold voltages, and increased j unction leakage current are emerging for memory cell transistors. With conv entional technology for fabricating memory cell transistors, it seems to be difficult to go beyond the 0.15-mum generation. Recently, a few exotic app roaches were proposed, but they should be further verified. In this work, a conventional structure with a rapid thermal annealing (RTA) process was de veloped to extend the conventional scheme down to the 0.13-mum technology g eneration.