A 3.3-V 12-bit high-speed current cell matrix CMOS DAC

A 3.3 V 65 MHz 12-bit CMOS current-mode DAC (Digital to Analog Converter) w as designed with a 8 MSB (Most Significant Bit) current matrix stage and a 4 LSB (Least Significant Bit) binary weighting stage. The linearity errors caused by the voltage drop of the ground line and by the threshold voltage mismatch of the transistors were reduced by using the symmetrical routing m ethod with ground line and a tree structure bias circuit, respectively. In order to realize a low glitch energy, we employed a cascode current switch. The simulation results for the designed DAC showed a conversion rate of 65 MHz, a power dissipation of 71.7 mW, a DNL (Differential Nonlinearity) of +/-0.5 LSB and an INL (Integral Non-linearity) of +/-2.0 LSB with a single power supply of 3.3 V for a 0.6-mum n-well CMOS technology.