Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level pa ckaging (WLP) manufacturing in order to raise assembly efficiencies and low er operating costs. Texas Instruments (TI) has developed a unique WLP proce ss for forming flip-chip, ball grid array packages. The die inputs and outp uts of the TI CSP are connected through solder bumps to a polyimide film in terposer. Solder balls on the other side of the interposer complete the ele ctrical connection to a customer's printed circuit board. A wafer-sized arr ay of interposers designed to match the pattern of dies on a wafer is align ed and reflowed to a bumped wafer. The TI WLP process is completed by singu lating the CSPs from the wafer using standard wafer saw equipment. Attachment of the interposer to the die as well as applying the die and boa rd level solder bumps are carried out in wafer form using a new bumping tec hnology called Tacky Dots (TM). Tacky Dots uses an array of sticky dots for med in a photosensitive coating laminated to a polyimide film for transferr ing and attaching solder spheres to semiconductor substrates. A populated f ilm containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow pro cess transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen. This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optim izing the design of the package is outlined. The paper concludes by summari zing the current package level reliability results. (C) 2001 Elsevier Scien ce Ltd. All rights reserved.