Power optimization of delay constrained circuits

We present a framework for combining Voltage Scaling (VS) and Gate Sizing ( GS) techniques for power optimizations. We introduce a fast heuristic for c hoosing gates for sizing and voltage scaling such that the total power is m inimized under delay constraints, We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the sh ort circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform bette r than the techniques applied in isolation. An average power reduction of 7 3% is obtained when decisions are taken assuming dynamic power only. In con trast, average power reduction is 77% when decisons include the short circu it power dissipation.