Accurate power estimation for sequential CMOS circuits using graph-based methods

We present a novel method for estimating the power of sequential CMOS circu its. Symbolic probabilistic power estimation with an enumerated state space is used to estimate the average power switched by the circuit. This approa ch is more accurate than simulation based methods. Automatic circuit partit ioning and state space exploration provide improvements in run-time and sto rage requirements over existing approaches. Circuits are automatically part itioned to improve the execution time and to allow larger circuits to be pr ocessed. Spatial correlation is dealt with by minimizing the cutset between partitions which tends to keep areas of reconvergent fanout in the same pa rtition. Circuit partitions can be recombined using our combinational estim ation methods which allow the exploitation of knowledge of probabilities of the circuit inputs. We enumerate the state transition graph (STG) incremen tally using state space exploration methods developed for formal verificati on, Portions of the STC are generated on an as-needed basis, and thrown awa y after they are processed. BDDs are used to compactly represent similar st ates. This saves significant space in the storage of the STG. Our results s how that modeling the state space is imperative for accurate power estimati on of sequential circuits, partitioning saves time, and incremental state s pace exploration saves storage space. This allows us to process larger circ uits than would otherwise be possible.