An instruction-level power analysis model with data dependency

Power constraints are becoming a critical design issue in the field of port able microprocessor systems. The impact of software on overall system power is becoming increasingly important as more and more digital applications a re implemented as embedded systems, part of which are hardware (ASICs) and part software in which a specific application is executed on a processor. I n this paper, a data-dependent instruction-level power analysis model is pr esented. It is compared with the average cost model proposed by Tiwari et a l. [1] in both estimation accuracy and characterisation time, The data-depe ndent model can be generalised to be applied to generic RISC processor. App lication of the data-dependent model we propose sensibly reduces errors in estimating software power consumption per clock cycle which is lower than 1 0%, in the case of the ST20-C2P core.