Statistical method for the analysis of interconnects delay in submicrometer layouts

In deep-submicrometer layouts, the determination of the signal delay due to interconnects is a main aspect of the design. Usually, on-chip interconnec ts are modeled by a distributed resistance-capacitance (RC) line. Key aspec ts of the interconnect modeling are the extraction of parasitic capacitance s and the determination of reduced lumped models suited for electrical simu lation, This paper addresses both these aspects, The parasitic capacitance extraction problem of layouts is efficiently carried out by means of the fl oating random walk (FRW) algorithm. It is shown how the employment of the M onte Carte integration jointly to an extended version of the FRW algorithm allows to directly synthesize an accurate reduced-order RC equivalent net, The new method can deal with very complex geometries in an efficient way an d needs neither fracturing of the original layout into subregions nor discr etization of interconnects.