Testing of scan circuits containing nonisolated random-logic legacy cores

We consider issues related to the testing of a random-logic legacy core emb edded in user-defined logic. We assume that the only information available about the core is its test set. We develop a model for the core and the sur rounding logic and provide procedures for testing the core and its surround ing logic under this model without adding design-for-testability (DFT) logi c (such as a test wrapper). The procedures maximize the information extract ed from the test set given for the core in order to maximize the fault cove rage achieved without DFT. This maximizes the ability to test the circuit a t-speed through its functional paths that go through cores and user-defined logic, We also describe DFT insertion procedures, The core and the surroun ding logic are considered simultaneously during DFT insertion to minimize t he amount of DFT logic required. We consider combinational logic (correspon ding to full-scan) as well as sequential logic.