OCCOM - Efficient computation of observability-based code coverage metricsfor functional verification

Functional simulation is still the primary workhorse for verifying the func tional correctness of hardware designs, Functional verification is necessar ily incomplete because it is not computationally feasible to exhaustively s imulate designs. It is important, therefore, to quantitatively measure the degree of verification coverage of the design, Coverage metrics proposed fo r measuring the extent of design verification provided by a set of Function al simulation vectors should compute statement execution counts (controllab ility information) and check to see whether effects of possible errors acti vated by program stimuli can be observed at the circuit outputs (observabil ity information). Unfortunately the metrics proposed thus far either do not compute both types of information or are inefficient, i.e., the overhead o f computing the metric is very large. In this paper, we provide the details of an efficient method to compute an observability-based code coverage met ric that can be used while simulating complex hardware description language (HDL) designs, This method offers a more accurate assessment of design ver ification coverage than line coverage and is significantly more computation ally efficient than prior efforts to assess observability information becau se it breaks up the computation into two phases: functional simulation of a modified HDL model followed by analysis of a flowgraph extracted from the HDL model, Commercial HDL simulators can be directly used for the time-cons uming first phase and the second phase can be performed efficiently using c oncurrent evaluation techniques.