Optimized programming of multilevel flash EEPROMs

The trade-off between speed and dispersion of programmed threshold voltages is investigated in 0.25 mum Flash memory technology, It is shown that ramp ed gate programming provides tighter distributions of programmed threshold voltages than its conventional Box-Waveform counterpart, allowing to write a larger number of bls, In particular, at low programming speed ramped gate programming is shown to allow four level schemes without program and verify operations, with a pro gram bandwidth potentially approaching 30 Mb/s in the conventional 1-b-per- cell scheme land correspondingly higher values in the multilevel case). Ins tead, sixteen level schemes without program and verify do not seem practica lly feasible.