Device level modeling of metal-insulator-semiconductor interconnects

Citation
Gf. Wang et al., Device level modeling of metal-insulator-semiconductor interconnects, IEEE DEVICE, 48(8), 2001, pp. 1672-1682
Citations number
30
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
48
Issue
8
Year of publication
2001
Pages
1672 - 1682
Database
ISI
SICI code
0018-9383(200108)48:8<1672:DLMOMI>2.0.ZU;2-5
Abstract
A rigorous model for metal-insulator-semiconductor (MIS) interconnects is p resented based on device level simulation results. At the device level, the motion equations of charged carriers and Maxwell's equations are simultane ously solved using a finite element scheme and Newton's method, Simulations provide detailed information regarding field-carrier interactions, semicon ductor substrate loss and nonlinearity, as well as slow-wave effect, extern al bias effect, and screening effect of the charged carriers. An equivalent circuit model of MIS interconnects is established using an energy-based ap proach. The model consists of an equivalent transmission line that mimics t he energy transport characteristics of the actual MIS interconnect, and pro vides a generalized nonlinear and electronic tunable circuit model suitable for both small-signal and large-signal analysis. Examples are presented to illustrate capabilities and efficiency of the method as well as properties of the equivalent circuit model.