Short-channel vertical sidewall MOSFETs

Vertical MOSFETs have been proposed in the roadmap of semiconductors as a c andidate for sub-100-nm CMOS technologies. In this paper, vertical n-channe l MOSFETs with channel length down to 50 nm are presented, fabricated in a standard production line with i-line lithography, A process flow using side wall gates and implantations instead of multiple layer depositions reduces process complexity and offers better CMOS compatibility. With this particu lar vertical MOSFET structure, called the vertical sidewall MOSFET, high do ping concentrations in the channel are needed for sub-100-nm devices, The u niform channel doping is more critical for vertical transistors than for a planar technology, where optimized profiles can he easier implemented. Ther efore, we investigated vertical MOSFETs with high channel doping concentrat ion up to 1 x 10(19) cm(-3) and channel lengths down to 50 nm, The impact o f the high doping levels on threshold voltage and on tunneling currents is discussed. Finally, by using slight process modifications first results on vertical double-gate MOSFETs will be presented, which in principle can oper ate with an undoped channel region.