A circuit-level perspective of the optimum gate oxide thickness

A performance constrained minimum power-area optimization is introduced to project the physical gate oxide thickness (t(OX)) scaling limit from a circ uit-level perspective, The circuit optimization is based on the recent phys ical alpha-power law MOSFET model that enables predictions of CMOS circuit performance for future generations of technology. The model is utilized to derive an equation for propagation delay including the transition time effe ct, A physical compact gate-tunneling current model is also derived to anal yze ultrathin oxide layers. Results indicate that the gate-tunneling power is substantially less (<5%) than the drain-to-source leakage power at the o xide thickness required for optimum CMOS logic circuit performance. As tox is scaled below 3.0 nm, the MOSFET performance improvement resulting from t ox scaling diminishes due to an increasing effect of the polysilicon gate d epletion depth on the electrical effective oxide thickness. The gate-tunnel ing power, however, remains exponentially dependent on t(OX), thus resultin g in an optimal value of t(OX) where the gate-tunneling power is negligible in comparison to the drain-to-source leakage power. The scaling limit of t (OX) is projected as 2.2, 1.9, and 1.4 nm for the 180, 150, and 100 nm tech nology generations, respectively.