Full CMP integration of CVD TiN damascene sub-0.1-mu m metal gate devices for ULSI applications

Authors
Ducroquet, F Achard, H Coudert, F Previtali, B Lugand, JF Ulmer, L Farjot, T Gobil, Y Heitzmann, M Tedesco, S Nier, ME Deleonibus, S
Citation
F. Ducroquet et al., Full CMP integration of CVD TiN damascene sub-0.1-mu m metal gate devices for ULSI applications, IEEE DEVICE, 48(8), 2001, pp. 1816-1821
Citations number
14
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
48
Issue
8
Year of publication
2001
Pages
1816 - 1821
Database
ISI
SICI code
0018-9383(200108)48:8<1816:FCIOCT>2.0.ZU;2-N
Abstract
Full chemical mechanical polishing (CMP) process integration of a W/TiN dam ascene metal gate has been optimized and is demonstrated to be compatible w ith ULSI circuit fabrication. Highly uniform and reliable electrical charac teristics are achieved for widely ranged MOS pattern structures (from 0.1-m um gate transistors up to 0.6-mm(2) capacitors). CVD TiN film as damascene gate electrode shows excellent properties for MOS performances and gate oxi de integrity even on ultrathin gate oxide (2-nm SiO2).