Low power digital multimedia telecommunication designs

The increasing prominence of wireless multimedia systems and the need to li mit power capability in very-high density VLSI chips have led to rapid and innovative developments in low-power design. Power reduction has emerged as a significant design constraint in VLSI design. The need for wireless mult imedia systems leads to much higher power consumption than traditional port able applications. This paper presents possible optimization technique to r educe the energy consumption for wireless multimedia communication systems. Four topics are presented in the wireless communication systems subsection which deal with architectures such as PN acquisition, parallel correlator, matched filter and channel coding. Two topics include the IDCT and motion estimation in multimedia application. These topics consider algorithms and architectures for low power design suc h as using hybrid architecture in PN acquisition, analyzing the algorithm a nd optimizing the sample storage in parallel correlator, using complex matc hed filter that analog operational circuits controlled by digital signals, adopting bit serial arithmetic for the ACS operation in viterbi decoder, us ing CRC to adaptively terminate the SOVA iteration in turbo decoder, using codesign in RS codec, disabling the processing elements as soon as the dist ortion values become great than the minimum distortion value in motion esti mation, and exploiting the relative occurrence of zero-valued DCT coefficie nt in IDCT.