Current mobile phone applications demand high performance from the DSP, and
future generations are likely to require even greater throughput. However,
it is important to balance these processing demands against the requiremen
t of low power consumption for extended battery lifetime. A novel low-power
digital signal processor (DSP) architecture CADRE (Configurable Asynchrono
us DSP for Reduced Energy) addresses these requirements through a multi-lev
el power reduction strategy. A parallel architecture and configurable compr
essed instruction set meets the throughput requirements without excessive p
rogram memory bandwidth, while a large register file reduces the cost of da
ta accesses. Sign-magnitude representation is used for data, to reduce swit
ching activity within the datapath. Asynchronous design gives fine-grained
activity control without the complexities of clock gating, and gives low el
ectromagnetic interference. Finally, the operational model of the target ap
plication allows for a reduced interrupt structure, simplifying processor d
esign by avoiding the need for exact exceptions.