Exploiting data-dependencies in ultra low-power DSP arithmetic

Strategies for the design of ultra low power multipliers and multiplier-acc umulators are reported. These are optimized for asynchronous applications b eing able to take advantage of data-dependent computation times. Neverthele ss, the low power consumption can be obtained in both synchronous and async hronous environments. Central to the energy efficiency is a dynamic-logic t echnique termed Conditional Evaluation which is able to exploit redundancie s within the carry-save array and deliver energy consumption which is also heavily data-dependent. Energy efficient adaptations for handling two's complement operands are int roduced. Area overheads of the proposed designs are estimated and transisto r level simulation results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given. Normalized comparisons with other designs show our approach to use less ene rgy than other published multipliers.