A novel low-power shared division and square-root architecture using the GST algorithm

Although SRT division and square-root approaches and GST division approach have been known for long time, square-root architectures based on the GST a pproach have not been proposed so far which do not require a final division /multiplication of the scale factor. A CST square-root architecture is deve loped without requiring either a multiplication to update the scaled square -root quotient in each iteration or a division/ multiplication by the scali ng factor after completing the square-root iterations. Additionally, quanti tative comparison of speed and power consumption of GST and SRT division/sq uare-root units are presented. Shared divider and square-root units are des igned based on the SRT and the GST approaches, in minimally and maximally r edundant radix-4 representations. Simulations demonstrate that the worst-ca se overall latency of the minimally-redundant GST architecture is 35% small er compared to the SRT. Alternatively, for a fixed latency, the minimally-r edundant GST architecture based division and square-root operations consume 32% and 28% less power, respectively, compared to the maximally-redundant SRT approach.