A low power FIR filter design for image processing

In this paper, a new low power design method of the FIR filter for image pr ocessing is proposed. Because the correlation between adjacent pixels is ve ry high in image data, the clock gating technique can be a good candidate f or low power strategy. However, the conventional clock gating strategy that is applied independently to every flip-flop of the filter give rise to too much additional area overhead and couldn't get a good result in the power reduction. In our method, each tap register, which is used to delay the inp ut data in the filter, is partitioned into two sub-registers according to t he correlation characteristic of its input space. For the sub-register whic h highly correlated data is inputted into, the dynamic power consumption is reduced by diminishing switching activity of the clock signal. We can also reduce the additional hardware overhead by propagating the clock gating co ntrol signal of the first tap register to other tap registers. To identify the efficiency of the proposed design method, we perform the experiments on some filters that are designed in VHDL. The power estimation tool says tha t the proposed method can reduce the power dissipation of the filter by mor e than 18% compared to the conventional filter design methods.