On mixed PTL/static logic for low-power and high-speed circuits

We present more evidence in a 0.25 mum CMOS technology that the pass-transi stor logic (PTL) structure that mixes conventional PTL structure with stati c logic gates can achieve better performance and lower power consumption co mpared to conventional PTL structure. The goal is to use the static gates t o perform both logic functions as well as buffering, Our experimental resul ts demonstrate that the proposed mixed PTL structure beats pure static stru cture and conventional PTL in 9 out of 15 test cases for either delay or po wer consumption or both in a 0.25 mum CMOS process. The average delay, powe r consumption, and power-delay product of the proposed structure for 15 tes t cases are 10% to 20% better of than the pure static implementations and u p to 50% better than the conventional PTL implementations.