Efficient low power/low swing bus design architectures

Novel low-power circuits based on low swing voltage technique, in the inter nal nodes of bus architectures, are proposed. Different classes of driver/r eceiver and repeater circuits are presented. They are implemented on conven tional CMOS technology. The proposed technique is based on inserting a vari able number of MOSFET transistors in the driver circuits, causing variable low swing voltage levels in the output of the driver circuits. In order to re-pull up the low swing voltage to full swing, innovated high-speed, cross -coupled latch voltage receiver circuits are proposed, In applications havi ng high load capacitance due to long interconnections, novel repeater circu its, based also on low swing voltage technique, are introduced. The differe nce between the values of threshold voltage of the nMOS transistor and the pMOS transistors is exploited to decrease the power dissipation. The effect of the proposed technique in noise margins is also analysed.